Title :
A modified reduced adder graph algorithm for multiplier block minimization in digital filters
Author :
Xu, Fei ; Chen, Jiajia ; Chang, Chip-Hong ; Jong, Ching-Chuen
Keywords :
Adders; Costs; Digital filters; Finite impulse response filter; Hamming weight; Logic; Minimization methods; Performance analysis; Signal processing algorithms; Table lookup;
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8660-4
DOI :
10.1109/APCCAS.2004.1412975
