Title :
Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops
Author :
Sarbishei, O. ; Maymandi-Nejad, M.
Abstract :
Clock overlap is an important issue in the design of sequential circuits and is typically avoided. In this paper we present a new power-efficient edge-triggered D flip-flop in which we have benefited from the overlap period of the clock signal. The design procedure of the proposed D flip-flop is presented. The performance of the flip-flop is compared with several state of the art flip-flops in a shift register and a pipeline adder in 0.18¿m CMOS technology. The proposed flip-flop has the lowest power-delay-product and consumes less area compared to others.
Keywords :
CMOS logic circuits; CMOS technology; Clocks; Energy consumption; Flip-flops; Latches; Logic circuits; Pipelines; Sequential circuits; Shift registers; Edge-triggered D flip-flops; charge-sharing; clock overlap; dynamic CMOS circuits; power-delay product;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA, USA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378818
