Title :
Fully integrated low power phase-locked loop for various inputs in sensor network applications
Author :
Gan, Jianhua ; Abraham, Jacob
Author_Institution :
Cirrus Logic Inc., Austin, TX, USA
Abstract :
A fully integrated low power phase-locked loop that locks to normal clocks and Manchester encoded data streams of different frequencies is presented. It can be used in various sensor network applications for clock recovery and synchronization between sensor nodes. The inputs to the phase and frequency detector can be normal clock or Manchester encoded data stream of 1,2, or 4 MHz. The on-chip loop filter can perform the filtering for different input frequencies. The output frequency is 32 MHz. The jitter is 300 ps and the power consumption is 3 mW at 3 V power supply.
Keywords :
integrated circuit design; jitter; low-power electronics; phase detectors; phase locked loops; sensors; synchronisation; 3 V; 3 mW; 300 ps; 32 MHz; Manchester encoded data stream; PLL; frequency detector; fully integrated low power phase-locked loop; jitter; normal clock recovery; on-chip loop filter; phase detector; power consumption; power supply; sensor network application; sensor node; synchronization; Clocks; Energy consumption; Filtering; Filters; Frequency synchronization; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Power supplies;
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN :
0-7803-8104-1
DOI :
10.1109/ACSSC.2003.1292344
