Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier

Author

Singh, Rahul ; Audet, Yves ; Gagnon, Yves ; Savaria, Yvon

Author_Institution

Dept. of Electr. Eng., Ecole Polytechnique de Montreal, Que.

fYear

2007

fDate

27-30 May 2007

Firstpage

709

Lastpage

712

Abstract

This article presents an application of a recently reported IC trimming technique using laser diffused resistors to reduce the input referred offset voltage of a precision amplifier. A three stage precision CMOS operational amplifier topology is proposed utilizing laser-trimmable diffused resistors for post-fabrication trimming. The amplifier is designed to operate over an industrial temperature range (-40degC to +85degC) including process corners and utilizes an on-chip CMOS bias generation circuit to maintain a robust performance. The results of post-layout simulation of the complete circuit are summarized. The effects of the trimming technique on the input offset voltage of the amplifier are described. The circuit is designed using the TSMC 0.18mum CMOS process and operates from a single supply of 3.3 V.

Keywords

CMOS analogue integrated circuits; integrated circuit design; operational amplifiers; -40 to 85 C; 0.18 micron; 3.3 V; CMOS operational amplifier topology; integrated circuit trimming; laser-trimmable diffused resistors; offset reduction; on-chip CMOS bias generation circuit; post-layout simulation; precision CMOS amplifier; Application specific integrated circuits; CMOS integrated circuits; CMOS process; Circuit simulation; Circuit topology; Operational amplifiers; Resistors; Robustness; Temperature distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.377907

Filename

4252733