VHDL Implementation of High-Performance and Dynamically Configures Multi-port Cache Memory

This paper presents the implementation of 64 x 64 multi-port Static Random Access Memory (SRAM) and newly proposed dynamically configured multi-port SRAM in VHDL (VHSIC hardware description language). It uses a dynamic memory partitioning algorithm where a VHDL test-bench is developed to verify the functionality of the dynamically configured memory. Results demonstrate that critical memory operations such as “read miss”, “write miss” and “write bypass” can be performed using newly proposed low power, area efficient dynamically configured memory.