Clock recovery and data recovery design for LVDS transceiver used in LCD panels

This work presents the design and implementation of a CDR (clock and data recovery) design for LVDS transceiver operations. Instead of using an oversampling scheme which requires a high-speed clock generator, we adopt an interpolation scheme which relaxes the demand of a high-speed PLL with a very high precision. A dual-tracking design is proposed to precisely align both edges of a data eye. Hence, the center of a data eye can be optimally sampled. A typical 0.25 μm 1P5M CMOS technology is used to realize the proposed dual-tracking CDR for 7×100 (bit-MHz) LVDS signaling. The post-layout simulation reveals that the worst-case jitter of the sampling clocks is less than 450 ps (peak-to-peak) and 250 ps (rms) at all process corners.