DocumentCode :
2892752
Title :
Multiplier architectures for media processing
Author :
Krithivasan, Shankar ; Schulte, Michael J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Volume :
2
fYear :
2003
fDate :
9-12 Nov. 2003
Firstpage :
2193
Abstract :
Media processing applications typically involve large amounts of data-level parallelism and operate on low-precision operands. This paper presents multiplier architectures for multimedia processing and compares them to conventional multiplier architectures for general-purpose processing in terms of area and delay. The proposed multiplier architectures support subword parallelism and additional features, which enhance their performance in multimedia applications, yet require only slightly more area and delay than conventional multipliers for general-purpose processing.
Keywords :
delays; multimedia communication; multiplying circuits; parallel processing; data-level parallelism; delay process; multimedia processing application; multiplier architecture; performance enhancement; subword parallelism; Application software; CMOS technology; Computer architecture; Concurrent computing; Data engineering; Data structures; Delay estimation; Digital signal processing; Encoding; Parallel processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN :
0-7803-8104-1
Type :
conf
DOI :
10.1109/ACSSC.2003.1292369
Filename :
1292369
Link To Document :
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