Title :
A taxonomy of parallel prefix networks
Author_Institution :
Sun Microsyst. Lab., Harvey Mudd Coll., Claremont, CA, USA
Abstract :
Parallel prefix networks are widely used in high-performance adders. Networks in the literature represent tradeoffs between number of logic levels, fanout, and wiring tracks. This paper presents a three-dimensional taxonomy that not only describes the tradeoffs in existing parallel prefix networks but also points to a family of new networks. Adders using these networks are compared using the method of logical effort. The new architecture is competitive in latency and area for some technologies.
Keywords :
adders; parallel architectures; fanout; high-performance adder; logic level; parallel prefix network; three-dimensional taxonomy; wiring track; Adders; Circuits; Computer architecture; Delay; Educational institutions; Laboratories; Logic; Sun; Taxonomy; Wiring;
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on
Print_ISBN :
0-7803-8104-1
DOI :
10.1109/ACSSC.2003.1292373
