A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL

Author

Pavlovic, Nenad ; Bergervoet, Jos

Author_Institution

NXP Semicond., Eindhoven, Netherlands

fYear

2011

fDate

20-24 Feb. 2011

Firstpage

54

Lastpage

56

Abstract

Advanced deep-submicron CMOS processes are well-suited for a digital implementation of phase-locked loop-(PLL) based frequency synthesizers. Recently, several RF all-digital phase-locked loops (ADPLL) have been reported. While ADPLLs come close to achieving the phase-noise performance of analog PLLs, the in-band spur level requirement is still challenging. In this paper we present a new digital-to-time-converter-(DTC) based ADPLL architecture where the time resolution can be easily scaled.

Keywords

CMOS integrated circuits; digital phase locked loops; digital-analogue conversion; frequency synthesizers; integrated circuit noise; phase noise; radiofrequency integrated circuits; ADPLL architecture; RF all-digital phase-locked loop; advanced deep-submicron CMOS process; analog PLL; digital-to-time-converter; fractional-N all-digital PLL; frequency 5.3 GHz; frequency synthesizer; in-band spur level requirement; phase-noise performance; time resolution; Detectors; Image edge detection; Jitter; Phase locked loops; Phase noise; Radiation detectors; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-61284-303-2

Type

conf

DOI

10.1109/ISSCC.2011.5746216

Filename

5746216