Title :
A 2.5GHz 32nm 0.35mm2 3.5dB NF −5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection
Author :
Fu, Chang-tsung ; Lakdawala, Hasnain ; Taylor, Stewart S. ; Soumyanath, Krishnamurthy
Author_Institution :
Intel, Hillsboro, OR, USA
Abstract :
In this paper, a 2.5GHz fully differential tuned LNA with integrated T/R switch is designed in a High-K metal gate 32nm digital CMOS process, and packaged in an SoC-compatible flip-chip package. Reliability constraints of the package severely limit the ability to depopulate soldering bumps, and RF components must be designed taking the bump location into account. The LNA achieves a 3.5dB NF, -5dBm P1dB at 2.5GHz while drawing 11 mA from a 1.8V supply. LNA performance is enabled by use of a push-pull topology that exploits the equal strength of p and n transistors to improve linearity, use of nested coupled inductors (NCI) for low-noise input matching and to reduce area. The T/R switch handles 34dBm of power with an insertion loss of 1.1dB at 2.5GHz. T/R switch performance is enabled by reuse of LNA gate inductor to enable low RX mode loss, use of remote body-contact ed TX switch with high power handling and ESD protection for a transformer coupled PA.
Keywords :
CMOS integrated circuits; circuit reliability; differential amplifiers; flip-chip devices; low noise amplifiers; network topology; system-on-chip; transistors; CMOS push-pull LNA; ESD protection; SoC-compatible flip-chip package; T/R switch; digital CMOS process; frequency 2.5 GHz; nested coupled inductors; push-pull topology; reliability; size 32 nm; transistors; Electrostatic discharge; Inductors; Logic gates; Noise measurement; Switches; Switching circuits; Transistors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746217