The "quiet" state-a new approach to low-power multiplier design

This paper proposes a novel implementation of the (4:2) redundant adder, which takes advantage of a "don\´t care" state to introduce a "quiet" state that suppresses glitch propagation in a multiplier\´s reduction tree. Simulations show that using two 32-bit random words, without Booth encoding, as much as a 10% reduction in driven capacitance can be achieved, which could translate to larger power savings due to the smaller switching activity at the adder\´s output wires.