A VHDL library of LNS operators

Author

Detrey, Jérémie ; De Dinechin, Florent

Author_Institution

LIP, ENS Lyon, France

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

2227

Abstract

Logarithmic number system (LNS) have been shown to be a competitive replacement of floating-point (FP) arithmetic, for precisions up to 32 bits. This paper presents a library of LNS operators aimed at smaller precisions typical of DSP applications. The novelty of our approach is the use of multipartite table compression in the addition and subtraction operators. The paper compares this approach to other published implementations, and to similar FP operators. The operators have been developed and tested on FPGAs, but they are written in fairly standard VHDL. They are available for download from www.ens-lyon.fr/LIP/Arenaire.

Keywords

digital signal processing chips; field programmable gate arrays; floating point arithmetic; hardware description languages; mathematical operators; DSP application; FPGA; LNS operator; VHDL library; addition-subtraction operator; digital signal processing; field programmable gate array; floating-point arithmetic; logarithmic number system; multipartite table compression; Arithmetic; Delay; Digital signal processing; Equations; Field programmable gate arrays; Interpolation; Libraries; Polynomials; Testing; World Wide Web;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292376

Filename

1292376