Title :
Erasing Bit Nodes on the Bipartite Graph for Enhanced Performance of LDPC Codes
Author :
Catherine, P.C. ; Soyjaudah, K.M.S.
Author_Institution :
Electr. & Electron. Dept., Univ. of Mauritius, Reduit, Mauritius
Abstract :
The proposed work is based on the fact that the complete set of bit nodes for an LDPC code may not always be required at the receiving side for successful decoding. A corresponding strategy is therefore built up. In contrast to common practice, the total number of iterations available is shared among different sets. The first set runs the decoding algorithm with all its bit nodes. Successive sets (in case of decoding failure) runs each with a different selection of "erased" bit nodes, leading to an overall non-monotonic behavior. The end result is a system capable of effectively dealing with the problem of cycles and trapping sets without even being aware of their existence. Reported results show an important coding gain over conventional systems.
Keywords :
decoding; graph theory; iterative methods; parity check codes; Bipartite graph; LDPC codes; bit nodes; decoding algorithm; iterations; trapping sets; Bipartite graph; Charge carrier processes; Decoding; Entropy; Integrated circuits; Iterative decoding; Coding Theory; LDPC Codes;
Conference_Titel :
Emerging Trends in Engineering and Technology (ICETET), 2011 4th International Conference on
Conference_Location :
Port Louis
Print_ISBN :
978-1-4577-1847-2
DOI :
10.1109/ICETET.2011.45