DocumentCode
2892915
Title
Erasing Bit Nodes on the Bipartite Graph for Enhanced Performance of LDPC Codes
Author
Catherine, P.C. ; Soyjaudah, K.M.S.
Author_Institution
Electr. & Electron. Dept., Univ. of Mauritius, Reduit, Mauritius
fYear
2011
fDate
18-20 Nov. 2011
Firstpage
107
Lastpage
111
Abstract
The proposed work is based on the fact that the complete set of bit nodes for an LDPC code may not always be required at the receiving side for successful decoding. A corresponding strategy is therefore built up. In contrast to common practice, the total number of iterations available is shared among different sets. The first set runs the decoding algorithm with all its bit nodes. Successive sets (in case of decoding failure) runs each with a different selection of "erased" bit nodes, leading to an overall non-monotonic behavior. The end result is a system capable of effectively dealing with the problem of cycles and trapping sets without even being aware of their existence. Reported results show an important coding gain over conventional systems.
Keywords
decoding; graph theory; iterative methods; parity check codes; Bipartite graph; LDPC codes; bit nodes; decoding algorithm; iterations; trapping sets; Bipartite graph; Charge carrier processes; Decoding; Entropy; Integrated circuits; Iterative decoding; Coding Theory; LDPC Codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging Trends in Engineering and Technology (ICETET), 2011 4th International Conference on
Conference_Location
Port Louis
ISSN
2157-0477
Print_ISBN
978-1-4577-1847-2
Type
conf
DOI
10.1109/ICETET.2011.45
Filename
6120564
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