Parallel Concatenation of LDPC Codes with Two Sets of Source Bits

Conventional attempts at using parallel concatenation for LDPC codes have not been widely successful. Interestingly, existing schemes do not rely on the concatenating architecture, but rather on the complementary profile of two carefully selected component codes. Each code individually drive the decoding process over the signal-to-noise ratio range over which it excels. In this work however, a concatenating scheme is proposed that is not limited by specific choices of component codes. In addition, the scheme also departs from conventional turbo style settings by transmitting two sets of source bits over the channel, instead of just one. At the receiving side then, two decoders are set up and share extrinsic information. The key difference however with the conventional turbo style, is that the channel information (being independent for both decoders) is not removed when computing the extrinsic information. As signal-to-noise ratio increases, the associated impact of this modification results in a valuable performance gain.