Title :
A 32nm Westmere-EX Xeon® enterprise processor
Author :
Sawant, Shankar ; Desai, Utpal ; Shamanna, Gururaj ; Sharma, Lokesh ; Ranade, Mandar ; Agarwal, Anil ; Dakshinamurthy, Sampath ; Narayanan, Rajagopal
Author_Institution :
Intel, Bangalore, India
Abstract :
The next-generation enterprise Xeon® processor consists of 10 Westmere 32nm cores and a shared inclusive L3 cache (LLC) integrated on a monolith ic die, with link-based l/Os. This paper focuses on the innovations and circuit optimizations over the predecessor targeting idle power reduction, robust high-speed I/O links, and performance per watt improvements. The processor is implemented in 32nm CMOS using high-κ metal gate transistors and nine cop per interconnect layers.
Keywords :
CMOS integrated circuits; cache storage; integrated circuit interconnections; microprocessor chips; CMOS; L3 cache; LLC; Westmere-EX Xeon Enterprise processor; circuit optimizations; metal gate transistors; monolith IC die; robust high-speed I/O links; size 32 nm; Arrays; Clocks; Jitter; Logic gates; Program processors; Random access memory; Synchronization;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746225
