DocumentCode :
2893054
Title :
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU
Author :
Fischer, Tim ; Arekapudi, Srikanth ; Busta, Eric ; Dietz, Carl ; Golden, Michael ; Hilker, Scott ; Horiuchi, Aaron ; Hurd, Kevin A. ; Johnson, Dave ; McIntyre, Hugh ; Naffziger, Samuel ; Vinh, James ; White, Jonathan ; Wilcox, Kathryn
Author_Institution :
AMD, Fort Collins, CO, USA
fYear :
2011
fDate :
20-24 Feb. 2011
Firstpage :
78
Lastpage :
80
Abstract :
AMD\´s 2-core "Bulldozer" module contains 213 million transistors in an 11 metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture improves performance and frequency while reducing area and power compared to a previous AMD x86-64 CPU in the same process. To achieve these goals, the design reduced the number of F04 inverter delays/cycle by more than 20%, achieving higher frequencies in the same power envelope even with increased core counts. The 2-core CPU module area (including 2MB L2 cache) is 30.9mm2. The Bulldozer micro-architecture is cycle-based, using soft-edge flip-flops (SEF) to provide high-frequency performance, process variation tolerance, and low power consumption.
Keywords :
CMOS integrated circuits; flip-flops; microprocessor chips; silicon-on-insulator; 2-core Bulldozer module; 2MB L2 cache; 8-core CPU; Bulldozer microarchitecture; HKMG SOI CMOS process; SEF; SOI 2-core processor module; high-frequency performance; low power consumption; process variation tolerance; size 32 nm; soft-edge flip-flops; voltage 0.8 V to 1.3 V; Arrays; Central Processing Unit; Clocks; Latches; Program processors; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-61284-303-2
Type :
conf
DOI :
10.1109/ISSCC.2011.5746227
Filename :
5746227
Link To Document :
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