DocumentCode
2893118
Title
Clock generation for a 32nm server processor with scalable cores
Author
Li, Shenggao ; Krishnakumar, Ashwin ; Helder, Edward ; Nicholson, Roan ; Jia, Vivian
Author_Institution
Intel, Santa Clara, CA, USA
fYear
2011
fDate
20-24 Feb. 2011
Firstpage
82
Lastpage
83
Abstract
Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents the implementation of a clock system targeting low-power low-skew high-data throughput and low latency for a next-generation Xeon® server processor with scalable cores in a 32nm 9-metal digital CMOS process.
Keywords
CMOS integrated circuits; clocks; multiprocessing systems; clock generation; clock system; data transport latency; digital CMOS process; intercore data throughput; low-power low-skew high-data throughput; multicore enterprise processor; next-generation Xeon® server processor; scalable cores; size 32 nm; Clocks; Inductors; Jitter; Metals; Phase locked loops; Program processors; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-61284-303-2
Type
conf
DOI
10.1109/ISSCC.2011.5746229
Filename
5746229
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