Title :
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers
Author :
Riedlinger, R.J. ; Bhatia, Rachna ; Biro, L. ; Bowhill, Bill ; Fetzer, E. ; Gronowski, P. ; Grutkowski, T.
Author_Institution :
Intel, Fort Collins, CO, USA
Abstract :
The next generation in the Intel® Itanium® processor family, code named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium® Processor 9300 series (Tukwila). The new design integrates a ring-based system interface derived from portions of previous Xeon® and Itanium® processors, and includes 32MB of Last Level Cache (LLC). The processor is designed in Intel®´s 32nm CMOS technology utilizing high-K dielectric metal gate transistors combined with nine layers of copper interconnect. The 18.2x29.9mm2 die contains 3.1 billion transistors, with 720 million allocated to the eight cores. A total of 54MB of on die cache is distributed throughout the core and system interface. Poulson implements twice as many cores as Tukwila while lowering the thermal design power (TDP) by 15Wto 170W and increases the top frequency of the I/O and memory inter faces by 50% to 6.4GT/s.
Keywords :
CMOS integrated circuits; cache storage; microprocessor chips; transistors; CMOS technology; Intel Itanium processor; Poulson; Tukwila; Xeon processor; copper interconnect; high-K dielectric metal gate transistors; last level cache; memory size 32 MByte; memory size 54 MByte; mission-critical servers; ring-based system interface; size 18.2 mm; size 29.9 mm; size 32 nm; storage capacity 64 bit; Clocks; Logic gates; Monitoring; Pipelines; Power supplies; Program processors; Transistors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746230
