An injection-locked ring PLL with self-aligned injection window

In modern analog front-ends, there is an increasing demand on high performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked loops (PLLs) with jitter on the order of few picoseconds desirable. Unfortunately, due to stringent limit on die area, sometimes a PLL with a ring oscillator is the only choice. To get better phase noise, a wider loop bandwidth is needed to suppress the noise of the voltage-controlled oscillator (VCO). However, due to the discrete-time nature of the operations, the loop bandwidth is limited to one-tenth of the crystal oscillator (XTAL) frequency. One way to solve this problem is to use the injection-locking technique. This method exploits the clean reference clock but has several production problems. One is the frequency offset between injection signal and VCO, and this can be solved by using the injection-locked PLL architecture. However, extra loops are still needed to adjust the injection window due to on-chip variations. In this work, an injection-locked ring PLL (ILRPLL) architecture is proposed to solve this problem. Using the concept of sub-sampling PLL, the injection window is aligned automatically without feedback adjustment. A 432 MHz ILRPLL is realized in ATV/DTV system to justi fy this technique.