Title :
A 32-bit microprocessor with efficient testable designs, the TX2
Author :
Nozuyama, Yasuyuki ; Mitani, Hiroshi ; Fukumoto, Tetsuya ; Utsumi, Tohru ; Hashimoto, Kazuhiro
Author_Institution :
Semicond. Syst. Eng. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A 32-bit microprocessor, the TX2, with efficient testable designs, has been developed. For manufacturing test, a combination of powerful BISTs and parallel scan design is implemented. The BISTs achieve 100% functional coverage for ROM, RAM and PLA and 78% coverage of single stuck-at faults of the remaining part of the TX2 including redundant faults. Scan test vectors obtained by ATPG have enhanced the coverage to 84%. Total test time is less than 2 seconds. There are also a few circuits for efficient design verification. Moreover, for higher test quality, Idd.q test is implemented. Total area overhead is 6.9%
Keywords :
built-in self test; computer testing; integrated circuit testing; logic testing; microprocessor chips; 32 bit; BISTs; PLA; RAM; ROM; TX2; design verification; manufacturing test; microprocessor; parallel scan design; single stuck-at faults; testable designs; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Design engineering; Microprocessors; Power engineering and energy; Programmable logic arrays; Read only memory; Systems engineering and theory;
Conference_Titel :
TRON Project International Symposium, 1994., Proceedings of the 11th
Conference_Location :
Tokyo
Print_ISBN :
0-8186-6775-3
DOI :
10.1109/TRON.1994.378608
