DocumentCode
2893267
Title
A platform-based MPEG-4 advanced video coding (AVC) decoder with block level pipelining
Author
Wang, Shih-Hao ; Peng, Wen-Hsiao ; He, Yuwen ; Lin, Guan-Yi ; Lin, Chen-Yi ; Chang, Shih-Chien ; Wang, Chung-Neng ; Chiang, Tihao
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
1
fYear
2003
fDate
15-18 Dec. 2003
Firstpage
51
Abstract
We present a baseline MPEG-4 AVC (advanced video coding) decoder based on an optimized platform-based design methodology. With this methodology, we jointly optimize the software and hardware design of the decoder. Overall decoding throughput is increased by synchronizing the software and the dedicated co-processors. The synchronization is achieved at macroblock-level pipelining. In addition, we optimize the decoder software by enhancing the frame buffer management, boundary padding, and content aware inverse transform. To speed up motion compensation and inverse transform, which are the most computationally intensive modules, two dedicated acceleration modules are realized. For comparison, the proposed prototype decoder and MPEG-4 AVC reference decoder are evaluated on an ARM platform, which is one of most popular portable devices. Our experiments show that the throughput of the MPEG-4 reference decoder can be improved by 6 to 7 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5 frames per second (fps) for QCIF video sequences. With the dedicated accelerators, the overall throughput is increased by about 30% to reach 6.6 fps on the average and is up to 10.3 fps for slow motion video sequences.
Keywords
decoding; image sequences; motion compensation; optimisation; pipeline processing; synchronisation; transforms; video coding; AVC decoder; MPEG-4; acceleration modules; advanced video coding; block level pipelining; boundary padding; circuit design methodology; content aware inverse transform; frame buffer management; motion compensation; software optimization; synchronization; task partitioning; task scheduling; video sequences; Acceleration; Automatic voltage control; Decoding; Design optimization; Hardware; MPEG 4 Standard; Pipeline processing; Throughput; Video coding; Video sequences;
fLanguage
English
Publisher
ieee
Conference_Titel
Information, Communications and Signal Processing, 2003 and Fourth Pacific Rim Conference on Multimedia. Proceedings of the 2003 Joint Conference of the Fourth International Conference on
Print_ISBN
0-7803-8185-8
Type
conf
DOI
10.1109/ICICS.2003.1292411
Filename
1292411
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