A 10 Gb/s clock and data recovery circuit with binary phase/frequency detector using TSMC 0.35 μm SiGe BiCMOS process

This work describes the design, fabrication, and verification of a clock and data recovery circuit (CDR). This CDR circuit utilizes a full-rate Alexander-type phase detector along with a Pottbacker-type phase/frequency detector to extend the frequency acquisition range and to prevent false locking. During the locked state, Pottbacker-type phase/frequency detector automatically remains the average frequency of the input data rate. A two-stage delay-interpolating ring oscillator is used to generate in-phase and quadrature-phase clocks. Separated frequency control inputs for the proportional path and integral path are implemented. The CDR circuit was fabricated in TSMC 0.35 μm SiGe BiCMOS technology. Experimental results show 1.2 ps rms jitter and 5 ps peak-to-peak jitter generation by 2³¹-1 PRBS at a rate of 10 Gb/s. Jitter transfer bandwidth is about 5 MHz without jitter peaking and jitter tolerance has a moderate margin above the OC-192 mask. The circuit excluding the output buffers, dissipates 430 mW power at 3.3 V power supply. The die size including the pads is 1.6×1.6 mm².