Author_Institution :
Dept. of Electron. Eng., Rashtrasant Tukdoji Maharaj Nagpur Univ., Nagpur, India
Abstract :
Notice of Violation of IEEE Publication Principles
"Delayed Latching for data synchronization in GALS SOC"
by Vivek E. Khetade, Dr. S. S. Limaye
in the 2011 4th International Conference on Emerging Trends in Engineering and Technology (ICETET), 2011, pp. 247 - 252
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"High Rate Data Synchronization in GALS SoCs"
by Rostislav (Reuven) Dobkin, Ran Ginosar, and Christos P. Sotiriou in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, Issue 10, 2006, pp. 1063 - 1074
Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failure. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using Petri Net graph (PN) approach. When high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on delayed latching (DL), is described. DL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Decoupled input port and Decoupled- output port for Delayed Latching are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner. Here we present the Petri net models of the Globally Asynchronous and Locally Synchronous (GALS) architectures for speed independent (SI). The models are feed into Petrify to produce logic equations for gate level implementation of asynchronous circuit. The circuit is simulated on VCS and synthesized on Design compiler of Synopsys EDA tool.
Keywords :
Petri nets; asynchronous circuits; circuit simulation; computational complexity; failure analysis; risk management; synchronisation; system-on-chip; GALS SOC; Petri Net graph approach; Synopsys EDA tool; VCS; asynchronous interface controller complexity; circuit simulation; clock tree delay; compiler design; complex global timing constraint; data synchronization; decoupled output port; delayed latching; gate level implementation; globally asynchronous locally synchronous systems-on-chip; high data bandwidth; in-depth analysis; intermodular communication; logic equation; metastability risk; pausable clocking; speed independent; synchronization failure; technology-independent manner; Clocks; Delay; Integrated circuit modeling; Latches; Logic gates; Synchronization; System-on-a-chip; Asynchronous circuits; globally asynchronous; locally synchronous (GALS); synchronization; system-on-chip (SoC);
