DocumentCode
2893596
Title
Design for high throughput SHA-1 hash function on FPGA
Author
Kim, Jae-woon ; Lee, Hu-ung ; Won, Youjip
Author_Institution
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea
fYear
2012
fDate
4-6 July 2012
Firstpage
403
Lastpage
404
Abstract
In this paper, we propose SHA-1 architectures to achieve high-throughput hardware implementations. Two techniques such as loop unfolding and pre-processing were used for high-speed SHA-1 core design. The system is made of four sub-modules to increase throughput. Xilinx Virtex-6 FPGA is used for implementation. Implemented SHA-1 module achieves a throughput of 7.35 Gbps, and its behavior has been verified by connecting with Xilinx MicroBlaze soft processor.
Keywords
cryptography; field programmable gate arrays; logic design; SHA-1 architectures; Xilinx MicroBlaze soft processor; Xilinx Virtex-6 FPGA; bit rate 7.35 Gbit/s; high-speed SHA-1 core design; high-throughput SHA-1 hash function design; high-throughput hardware implementations; loop unfolding; pre-processing; Algorithm design and analysis; Computer architecture; Field programmable gate arrays; Hardware; Pipeline processing; Software algorithms; Throughput; SHA-1; hardware implementation; hash function;
fLanguage
English
Publisher
ieee
Conference_Titel
Ubiquitous and Future Networks (ICUFN), 2012 Fourth International Conference on
Conference_Location
Phuket
ISSN
2165-8528
Print_ISBN
978-1-4673-1377-3
Electronic_ISBN
2165-8528
Type
conf
DOI
10.1109/ICUFN.2012.6261737
Filename
6261737
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