DocumentCode :
2893647
Title :
10:4 MUX and 4:10 DEMUX gearbox LSI for 100-gigabit Ethernet link
Author :
Ono, Goichi ; Watanabe, Keiki ; Muto, Takashi ; Yamashita, Hiroki ; Fukuda, Koji ; Masuda, Noboru ; Nemoto, Ryo ; Suzuki, Eiichi ; Takemoto, Takashi ; Yuki, Fumio ; Yagyu, Masayoshi ; Toyoda, Hidehiro ; Kambe, Akihiro ; Saito, Tatsuya ; Nishimura, Shinji
Author_Institution :
Hitachi, Tokyo, Japan
fYear :
2011
fDate :
20-24 Feb. 2011
Firstpage :
148
Lastpage :
150
Abstract :
The authors presents a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI implemented in 65nm CMOS decreases power dissipation by 75% compared to that of a conventional LSI.
Keywords :
CMOS integrated circuits; integrated optoelectronics; large scale integration; multiplexing equipment; optical communication equipment; optical fibre LAN; 100GbE gearbox; CMOS; bit rate 100 Gbit/s; demultiplexer; gearbox LSI 100 gigabit Ethernet link; size 65 nm; CMOS integrated circuits; Clocks; Large scale integration; Phase locked loops; Power demand; Power dissipation; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-61284-303-2
Type :
conf
DOI :
10.1109/ISSCC.2011.5746258
Filename :
5746258
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2893647
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