DocumentCode

2893657

Title

The microarchitecture of a low power clustered register file for parallel processors

Author

Hua, Chung-Hsien ; Hwang, Wei

Volume

2

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

1029

Lastpage

1032

Keywords

CMOS technology; Capacitance; Delay estimation; Energy consumption; Microarchitecture; Power dissipation; Propagation delay; Registers; Silicon; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1413058

Filename

1413058