Realization of a systematic bit-wise decomposition metric

Author

Chang, Chia-Wei ; Chen, Po-Ning ; Han, Yunghsiang S.

Author_Institution

Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

2

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

1065

Abstract

A realization structure for our previously proposed systematic recursive formula for bit-wise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.

Keywords

OFDM modulation; binary codes; binary sequences; convolutional codes; interleaved codes; quadrature amplitude modulation; M-ary modulation; M-ary symbol metric; OFDM modulation; binary code; bitwise decomposition metric; convolutional codes; decoders; deinterleaver; information sequence; interleaved code; latency reduction; memory space reduction; quadrature amplitude modulation; realization structure; recursive formula; Circuits; Code standards; Computer science; Convolutional codes; Decoding; Delay; Error correction codes; OFDM modulation; Quadrature amplitude modulation; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1413067

Filename

1413067