Title :
The design of RS decoder with a small core for portable communication
Author :
Jing, M.-H. ; Truong, T.K. ; Chen, Y.H. ; Luo, Y.C.
Author_Institution :
Coll. of Electr. & Inf. Eng., I-Shou Univ., Kaohsiung, Taiwan
Abstract :
A new VLSI architecture using free discrepancy Berlekamp-Massey (FDBM) algorithm is proposed for wireless applications. Firstly, this project uses the FDBM algorithm to reduce the path delay. A method of module reuse is applied to reduce the overall core size successfully. Using single system clock, it is easy to integrate the core into SoC. As a result, this RS decoder has reduced core size and performs in low power with simple system integration.
Keywords :
Reed-Solomon codes; VLSI; hardware description languages; mobile communication; system-on-chip; RS decoder; SoC; VLSI architecture; Verilog HDL; core size reduction; free discrepancy Berlekamp-Massey algorithm; module reuse method; path delay reduction; portable communication; single system clock; wireless applications; Block codes; Clocks; Computer architecture; Decoding; Delay; Educational institutions; Electronic mail; Equations; Error correction codes; Polynomials;
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8660-4
DOI :
10.1109/APCCAS.2004.1413068
