A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz

The current-steering DACs are commonly used in generating high-frequency signals. A current-steering DAC comprises current cells of various sizes. Each of them contains a current source and a current switch. The DAC static linearity, specified as differential nonlinearity (DNL) and integral nonlinearity (INL), is mainly determined by the mutual matching and the output resistance of the current sources. The DAC also exhibits dynamic distortion. It is manifested as spurious-free dynamic range (SFDR) degradation. The SFDR decreases rapidly with increasing input frequency. There are two major sources of dynamic distortion, code-dependent switching transients (CDST) and code-dependent output-loading variation (CDLV). Switching transients are temporal disturbances in DAC out put when the current switches in current cells make transitions. The output load ing of a DAC varies when the output impedances of current cells change due to the transposition of their current switches. This DAC applies a digital random return-to-zero (DRRZ) technique to mitigate the CDST effect. Compact current cells are designed to minimize the CDLV effect. The current mismatches of the current cells are corrected by background calibration.