Title :
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory
Author :
Greshishchev, Yuriy M. ; Pollex, Daniel ; Wang, Shing-Chi ; Besson, Marinette ; Flemeke, Philip ; Szilagyi, Stefan ; Aguirre, Jorge ; Falt, Chris ; Ben-Hamida, Naim ; Gibbins, Robert ; Schvan, Peter
Author_Institution :
Ciena, Ottawa, ON, Canada
Abstract :
This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >;30dBc and EIIOB>;4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die area is less than 0.6x0.4 mm2.
Keywords :
CMOS integrated circuits; digital-analogue conversion; integrated circuit testing; CMOS; core DAC die area; size 65 nm; test circuit; total power dissipation; CMOS integrated circuits; Clocks; Digital signal processing; Frequency domain analysis; Integrated circuit interconnections; Logic gates; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746279
