Thermal Modeling and Temperature Driven Placement for FPGAs

With rapid technology scaling and increased use of FPGAs in mobile and low power applications, the effect of temperature on power, performance and reliability has become a challenge for system designers. In this work we make two major contributions to thermal aware design in FPGAs. First, we formulate a resistive mesh model for thermal profiling of FPGAs. The model exploits the characteristic features of the reconfigurable fabric to produce an efficient and accurate thermal estimate. We then employ the thermal model in a novel temperature driven placement tool for FPGAs. Our placement tool achieves an average temperature reduction of 2.26degC and produces a more uniform thermal distribution. The impact on frequency and wirelength is small with an average degradation of 5.28 and 4.15 percent respectively.