Author :
Sheu, Shyh-Shyuan ; Chang, Meng-Fan ; Lin, Ku-Feng ; Wu, Che-Wei ; Chen, Yu-Sheng ; Chiu, Pi-Feng ; Kuo, Chia-Chen ; Yang, Yih-Shan ; Chiang, Pei-Chia ; Lin, Wen-Pin ; Lin, Che-He ; Lee, Heng-Yuan ; Gu, Pei-Yi ; Wang, Sum-Min ; Chen, Frederick T. ; Su, Ke
Abstract :
This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random access time is presented. Multi-level-cell (MLC) operation with 160ns write-verify operation is demonstrated.
Keywords :
embedded systems; random-access storage; MLC-access capability; embedded RRAM; embedded SLC resistive-RAM macro; read-write random-access time; single-level-cell RRAM macro; Delay; Electrical resistance measurement; Nonvolatile memory; Phase change random access memory; Resistance; Sensors; Solid state circuits;
