95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm

This paper presents intelligent solid-state drives (SSDs), which decrease memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases, both data retention and program disturb errors increase due to the interference, random telegraph noise and reduced electrons. In the scaled NAND, the electric field in the channel increases and the program disturb due to GIDL-induced hot electron injection becomes more significant (Fig. 11.4.1(c)). In conventional SSDs, 20 to 40 b correction per 1 KB codeword error-correcting code (ECC) is used to correct errors. As stronger codes, such as LDPC, are developed, the capability of ECC is close to the Shannon limit of a few percent error correction. Thus, the additional high-reliability scheme is required. As the feature size decreases, the power consumption increases due to the increased bit-line capacitance of NAND. As the space between bitlines decreases, the inter bitline capacitance increases. To overcome reliability and power problems in SSDs, this paper describes two technologies. Asymmetric coding improves memory-cell reliability by 95% without access-time penalty. Stripe pattern elimination algorithm eliminates the worst program data pattern and decreases the power during the program by 43% without circuit area or access time overhead.