DocumentCode

2894228

Title

Parasitic effects in integrated circuits

Author

Dicken, H.

Author_Institution

Motorola Semiconductor Products, Inc., Phoenix, AZ, USA

Volume

VI

fYear

1963

fDate

20-22 Feb. 1963

Firstpage

98

Lastpage

99

Keywords

Circuit optimization; Circuit testing; Diffusion processes; Epitaxial layers; Fabrication; P-n junctions; Parasitic capacitance; Resistors; Silicon; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference. Digest of Technical Papers. 1963 IEEE International

Conference_Location

Philadelphia, PA, USA

Type

conf

DOI

10.1109/ISSCC.1963.1157449

Filename

1157449