DocumentCode :
2894267
Title :
Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder
Author :
Moskal, John ; Oruklu, Erdal ; Saniie, Jafar
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
fYear :
2007
fDate :
27-30 May 2007
Firstpage :
1089
Lastpage :
1092
Abstract :
The decimal arithmetic has been receiving an increased attention because of the growth of financial and scientific applications requiring high precision and increased computing power. This paper presents an efficient architecture for multi-digit decimal addition based on carry-free signed-digit numbers. In this study, the decimal adder architecture has been designed and synthesized using the TSMC 0.18mu technology. The synthesis results were compared to the existing decimal adders with respect to design area, delay and power consumption. These results show that proposed adder architecture improves the area-delay factor by 3 for a 32 digit adder.
Keywords :
adders; network synthesis; carry-free signed-digit decimal adder; decimal arithmetic; multidigit decimal addition; Adders; Application software; Circuit synthesis; Computer architecture; Costs; Delay; Digital arithmetic; Energy consumption; Floating-point arithmetic; Hardware;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
Type :
conf
DOI :
10.1109/ISCAS.2007.378199
Filename :
4252828
Link To Document :
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