High throughput 2-D transform architectures for H.264 advanced video coders

Author

Cheng, Zhan-Yuan ; Chen, Che-Hong ; Liu, Bin-Da ; Yang, Jar-Ferr

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

2

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

1141

Abstract

In this work, high throughput hardware architectures for fast computation of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC) are presented. After complexity and efficiency analyses, we find that the proposed architectures could provide higher throughput rate and realize in a smaller chip area than the conventional row-column approaches. The proposed architectures are synthesized with TSMC 0.35 μm technology. The synthesized multiple transform architecture could process 800 M samples/sec at 100 MHz for all the three transforms.

Keywords

Hadamard transforms; code standards; transform coding; video coding; 0.35 micron; 100 MHz; H.264 advanced video coders; Hadamard transforms; high throughput 2D transform architectures; high throughput hardware architectures; inverse transforms; multiple transform architecture; row-column methods; Automatic voltage control; Computer architecture; Discrete cosine transforms; Discrete transforms; Error correction; Error correction codes; Hardware; Technological innovation; Throughput; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1413086

Filename

1413086