Keynote: High performance computing based on FPGAS

Driven by the increasing demand of high performance computing (HPC) systems in scientific and commercial computing on one hand and the limitation of todays processor technology (memory wall, frequency wall, power wall) on the other hand there is a growing interest in highly scalable and high-performance computer architectures based on application-optimized processors and computation technology. Examples of specialized high-performance processors are graphic processing units (GPUs) and game processors, e.g. the Cell/B.E. processor, which are capable of performing more than the specific computations for which they were designed. A big challenge especially in HPC is to integrate those specialized processors into a system architecture which is able to provide the I/O and sustained system performance in a massively parallel computation system. An example is the worldpsilas fastest supercomputer with a peak performance of 1.7 petaflops which is a hybrid design based on standard dual-core and specialized game processors which are connected by a specific I/O expansion board. Another highly innovative and scalable computer design based on game processors is the so-called ldquoQCD parallel computer based on cell technologyrdquo (QPACE) which consists of an application-optimized network chip implemented on FPGA overcoming the I/O limitations of existing network chips. This talk will provide an overview and insight into the QPACE architecture concept with focus on the application-optimized network implemented on FPGAs and will discuss scalable computer design concepts in HPC based on specialized high performance processors.