Modeling recursion data structures for FPGA-based implementation

Recursion is a powerful technique used to solve problems with repeating patterns, and is a fundamental structure in software. To date there is no known general way to apply a recursive solution to reconfigurable hardware; it is considered difficult to implement, of low performance and resource-intensive. In this paper we extend previous results on hardware structures for recursion by V. Sklyarov, and we demonstrate that recursion can be efficiently implemented in a general way on FPGAs. We show that our general, non-optimized architecture presents approximately 3 times speedup against optimized software algorithm implementations. It also shows 75% speedup, at least 40% lower area utilization, and at the same time it is simpler, less designer time consuming and more general vs. previously published hardware implementations.