Title :
Fast toggle rate computation for FPGA circuits
Author :
Czajkowski, Tomasz S. ; Brown, Stephen D.
Author_Institution :
Dept. of ECE, Univ. of Toronto, Toronto, ON
Abstract :
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a CAD tool to identify the parts of the circuit that can benefit from power optimization. A key advantage of our approach is its ability to efficiently account for spatial correlation of related logic cones, which is accomplished using a novel XOR-based decomposition. In addition, our approach uses post-routing circuit delays to account for glitches in a logic circuit. The proposed approach was tested on 14 MCNC benchmark circuits compiled for the Altera Stratix II devices. The results indicate that our method improves the vectorless estimation technique available in the latest version of Alterapsilas Quartus II commercial CAD tool, reducing the average error by 37% and standard deviation by 59%.
Keywords :
CAD; delay circuits; field programmable gate arrays; logic circuits; optimisation; Altera Stratix II devices; FPGA circuits; MCNC benchmark circuits; Quartus II commercial CAD tool; XOR-based decomposition; logic circuit; logic cones; post-routing circuit delays; power optimization; scalable method; signal toggle rate computation; spatial correlation; vectorless estimation; Benchmark testing; Circuit testing; Costs; Delay; Field programmable gate arrays; Logic circuits; Logic devices; Power dissipation; Table lookup; Wire;
Conference_Titel :
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location :
Heidelberg
Print_ISBN :
978-1-4244-1960-9
Electronic_ISBN :
978-1-4244-1961-6
DOI :
10.1109/FPL.2008.4629909
