Title :
A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications
Author :
Osorio, Juan F. ; Vaucher, Cicero S. ; Huff, Bill ; Heijden, Edwin V d ; De Graauw, Anton
Author_Institution :
NXP Semicond., Eindhoven, Netherlands
Abstract :
This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.
Keywords :
3G mobile communication; CMOS digital integrated circuits; Long Term Evolution; field effect MIMIC; frequency dividers; frequency multipliers; frequency synthesizers; microwave links; multiplying circuits; personal area networks; phase locked loops; 3G-LTE base-station networks; CMOS process; IEEE 802.15.3c communication standard; PLL; divider-by-two circuit; frequency 21.7 GHz to 27.8 GHz; frequency multiplier-by-two circuit; frequency synthesizer; microwave links; mm-wave communication application; power dissipation; residual phase modulation; size 45 nm; sliding-IF configuration; CMOS integrated circuits; Frequency conversion; Frequency synthesizers; Phase locked loops; Phase noise; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-61284-303-2
DOI :
10.1109/ISSCC.2011.5746317
