Design and implementation of data synchronous system for merging unit based on FPGA

With the highly strict demand of data synchronicity in the protective device of substation, the merging unit´s synchronization delay, from data collecting to data sending, should be both short and stable. However, the calibration time is usually not precise in current substations. In order to solve the problem that sampling data is not synchronous, this paper designs a kind of system using FPGA based on Newton interpolation algorithm. This algorithm takes advantage of sampling information of the merging unit´s accurate arriving time and packet´s delay time to calculate the corresponding sample in local time. Then it can get the sample information of different merging units at the same local time using interpolation calculation. Compared with the traditional way, this method realizes sample value synchronization without external synchronous clock source. This system receives data from multiple merging units, and then sends to bay layer unit to use after data synchronization. In power system, the processed delay of sample value is less than 10us, which is really difficult for CPU. So FPGA is used in this system. Being adopted modular design to make each sub-module collateral execution, the speed level is ns. The simulation and experiment results demonstrate the validity of the proposed method, and this system is very meaningful and important to the automation development of the power system.