DocumentCode
2895208
Title
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
Author
Shelburne, M. ; Patterson, C. ; Athanas, P. ; Jones, M. ; Martin, B. ; Fong, R.
Author_Institution
Bradley Dept. of Electr.&Comput. Eng., Configurable Comput. Lab., Blacksburg, VA
fYear
2008
fDate
8-10 Sept. 2008
Firstpage
257
Lastpage
262
Abstract
While there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on an FPGA is already costly due to the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port (ICAP) and is shown to provide a bandwidth exceeding 200 MBytes/sec.
Keywords
delays; field programmable gate arrays; network-on-chip; ICAP; Virtex-4 Internal Configuration Access Port; Xilinx FPGA configuration circuitry; die resources; metawire; network-on-chip; time delays; Bandwidth; Circuits; Computer networks; Field programmable gate arrays; Hardware; Network interfaces; Network-on-a-chip; Reconfigurable logic; Routing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location
Heidelberg
Print_ISBN
978-1-4244-1960-9
Electronic_ISBN
978-1-4244-1961-6
Type
conf
DOI
10.1109/FPL.2008.4629941
Filename
4629941
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