Design of FFT processor with low power complex multiplier for OFDM-based high-speed wireless applications

Author

Jiang, Min ; Yang, Bing ; Fu, Yiling ; Jiang, Anping ; Wang, Xin-An ; Gan, Xuewen ; Zhao, Baoying ; Zhang, Tianyi

Author_Institution

Sch. of Comput. Sci. & Electr. Eng., Peking Univ., Beijing, China

Volume

2

fYear

2004

fDate

26-29 Oct. 2004

Firstpage

639

Abstract

We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.

Keywords

OFDM modulation; carry logic; digital signal processing chips; fast Fourier transforms; fixed point arithmetic; low-power electronics; mobile radio; tree data structures; CSA tree; DIT; OFDM; canonical signed digit; carry save add tree; constant complex multiplications; fixed-point FFT processor; high-speed wireless applications; low power complex multiplier; radix-2 butterfly algorithm; Amplitude modulation; Computational modeling; Computer architecture; Discrete Fourier transforms; Energy consumption; Hardware; Intensity modulation; Phase modulation; Process design; Quadrature amplitude modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on

Print_ISBN

0-7803-8593-4

Type

conf

DOI

10.1109/ISCIT.2004.1413792

Filename

1413792