Title :
Power-efficient design of memory-based FFT processor with new addressing scheme
Author :
Lee, Seungbeom ; Kim, Duk-Bai ; Park, Sin-Choug
Author_Institution :
Syst. Integration Technol. Inst., Inf. & Commun. Univ., Daejeon, South Korea
Abstract :
The paper presents a new memory-addressing scheme for the realization of low power FFT processors. The scheme is based on the minimization of coefficient access and the reduction of switching activity by modifying the butterfly sequence. Therefore, power consumption in the complex multiplier and memory is significantly saved.
Keywords :
digital signal processing chips; digital storage; fast Fourier transforms; hypercube networks; integrated circuit design; logic design; minimisation; power consumption; storage allocation; butterfly sequence; butterfly unit; coefficient access minimization; memory-addressing scheme; memory-based FFT processor; multiplier; power consumption; power-efficient design; switching activity reduction; Algorithm design and analysis; Communication switching; Communication system control; Computer architecture; Discrete Fourier transforms; Energy consumption; Fast Fourier transforms; Portable computers; Radar imaging; Random access memory;
Conference_Titel :
Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on
Print_ISBN :
0-7803-8593-4
DOI :
10.1109/ISCIT.2004.1413801
