An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology

The bandwidth limitation of existing backplanes has become an obstacle to meeting the increasing demand for high-data-rate wireline transmission. In order to compensate for this limitation, TX pre-emphasis, RX continuous-time linear equalizer (CTLE) and DFE are necessary. This work presents a 4-lane transceiver implemented in 40nm CMOS technology that operates over a wide range of data rates from 1 to 12Gb/s (48Gb/s aggregated) using NRZ coding. The supply voltages are 0.9V and 1.8V. An algorithm is developed to adapt the CTLE and DFE to cancel the channel ISI. No inductors are used in the design and ring oscillators are used for both the TX and RX clock generation. This provides a wide frequency-tuning range, small layout area, and high design portability. With extensive use of digital programmability this transceiver is capable of meet ing specifications of different standards, such as PCIe, SATA, and 1 to 10Gb/s Ethernet.