Title :
A novel charge recovery logic structure with complementary pass-transistor network
Author :
Jingyang Li ; Yimeng Zhang ; Yoshihara, Tatsuhiko
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
Abstract :
This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.
Keywords :
clocks; logic circuits; transistor circuits; 2-phase nonoverlap alternating power clock; complementary pass-transistor boost logic; complementary pass-transistor network; frequency 50 MHz to 500 MHz; low-power charge recovery logic structure; size 0.18 mum; word length 4 bit; CMOS integrated circuits; Clocks; Logic gates; Power dissipation; RLC circuits; Radiation detectors; Transistors; 4-bit counter; CPBL; Charge recovery logic; low power;
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
DOI :
10.1109/ISOCC.2012.6406914
