Design of high-speed support vector machine circuit for driver assistance system

In this paper, we propose a high-speed support vector machine (SVM) circuit for driver assistance system (DAS). By adopting a parallel architecture with pipeline, the circuit can provide real-time processing with a large amount of operations. The circuit can support both linear and non-linear SVM types by unifying their algorithms and architectures. The circuit size is minimized by sharing most of the resources required in the computation for both SVM types. We described the proposed high-speed SVM circuit using Verilog HDL and implemented an MPW chip using a 65nm standard cell library for silicon verification. Since the circuit can process 92 640×480 image frames per second, assuming three cameras installed on the vehicle, it can be used to provide real-time pedestrian and vehicle detection for DAS.