Title :
Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers
Author :
Gädke, Hagen ; Stock, Florian ; Koch, Andreas
Author_Institution :
Integrated Circuit Design, Tech. Univ. Braunschweig, Braunschweig
Abstract :
Control-memory-data flow graphs (CMDFGs) are a unified intermediate representation for compiling high-level languages onto reconfigurable adaptive computing systems. We present both their initial construction as well as transformations for parallel memory accesses. The impact on a number of applications is examined, also considering the effect of caches on acceleration efficiency.
Keywords :
data flow graphs; high level languages; program compilers; reconfigurable architectures; control-memory-data flow graphs; high-level language compilation; memory access parallelisation; parallel memory accesses; reconfigurable adaptive computers; reconfigurable adaptive computing systems; Acceleration; Adaptive control; Adaptive systems; Concurrent computing; Dynamic scheduling; Hardware; High level languages; Microarchitecture; Programmable control; Runtime;
Conference_Titel :
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location :
Heidelberg
Print_ISBN :
978-1-4244-1960-9
Electronic_ISBN :
978-1-4244-1961-6
DOI :
10.1109/FPL.2008.4629971
