Evaluating the effects of branch prediction accuracy on the performance of SMT architectures

Branch instruction occurrence reduces the parallelism exploited from the source code of single-threaded applications. In order to reduce the branch penalty, several branch predictor techniques have been proposed. Branch predictors allow the fetch unit to continue fetching instructions along a predicted path after a conditional branch has been detected. Such techniques, when used in conventional superscalar architectures, may reach more than 95% of accuracy. These same techniques are also used in SMT architectures. However, SMT architectures may have a different behavior due to the parallelism exploration in several threads. Moreover, the effects supported by one thread may influence also the performance of other threads. In this work, we vary the accuracy of the branch predictor in order to evaluate the impact on the performance of a SMT architecture. Even though the SMT and superscalar have a different behavior, we observed that the effect of the improvement in the prediction accuracy is similar for both architectures