Exploring compact design on high throughput coarse grained reconfigurable architectures

Aiming toward a compact high- throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we explain several methods, namely two data transfer methods and three feedback path methods, and provide an evaluation of the architecture. The evaluation results showed that the structure which allows for the smallest chip area comprises the dedicated wiring method for data transfer and the area effort method for routing. Further, the transistor count of the DS-HIE processor is notably smaller than that of the core 2 duo processor.